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? semiconductor MSM6542-01/02/03 68 description the msm6542 is a perpetual-calendar-based real time clock with an alarm function which can read and write data in units of seconds. it can be connected to various buses and can function as a peripheral ic of a microcom- puter. the clock ranges are seconds, minutes, hours, days, months, years, and days of the week. the alarm ranges are seconds, minutes, hours, days, months, and days of the week. an event trigger is generated when the time matches the specified time and an alarm oc- curs or when the clock counter generates a carry. the interrupt and pulse outputs are provided for each of an alarm and a carry. an interface with a microcomputer is imple- mented by four data bus pins, four address bus ? semiconductor MSM6542-01/02/03 real time clock with periodic and alarm output bus pins, three control bus pins, and two chip select pins. these pins are used to write or read data from the clock, alarm, and control registers, or to modify the data. the msm6542 has an address latch enable (ale) input pin, allowing the data bus and address bus to be shared. when the ale input pin is kept high, the data bus and ad- dress bus can be exclusively used. other functions of the msm6542 are: a 30- second adjustment, stop and restart of clock, data registers as ram, and data register (ram) protection. the cmos circuitry used in the msm6542 affords low power dissipation. the crystal oscillator operates at 32.768 khz. provisions for backup time keeping are included. features ? real time clock providing seconds, minutes, hours, days, months, years, and days of the week. ? multiple alarm ranges covering seconds, minutes, hours, days, months, and days of the week. a desired alarm range can be selected. ? a periodic interrupt output interval can be selected over a wide range from 1/1024 seconds up to 10 minutes. ? interface flexibility allows for connection to many types of microprocessors. ? single read-out procedure (read flag). ? single power sense circuitry. (data protect function). ? unused registers can be used as ram. ? 30-second adjustment by software or hardware (software only for the msm6542- 1/-2). ? stop and restart of clock by software or hardware (software only for the msm6542- 1/-2). ? 1 hz output for adjustment and check of oscillation frequency (msm6542-3 only). ? user selection of 12 or 24 hour clock mode. ? address latch enable (ale) input pin. ? advanced cmos circuitry allows low stand-by voltage and current. ? user standard 32.768 khz oscillator crys- tal ? available in multiple packages 18-pin plastic dip (for the msm6542- 1rs/2rs) (dip18-p-300). 20-pin plastic sop (for the msm6542- 1ms-k/2ms-k) (ssop20-p-250-k). 24-pin plastic dip (for the msm6542- 3rs) (dip24-p-600). 24-pin plastic sop (for the msm6542- 3gs-vk) (sop24-p-430-vk). ? pin assignment compatibility with the msm6242brs (the msm6542-3msk pro- vides near compatibility.).
? semiconductor MSM6542-01/02/03 69 interrupt out 1 2 3 4 5 6 7 8 9 18 17 16 14 13 12 11 10 ale 15 e v ss xt xt r/ w a 1 a 0 a 2 a 3 d 0 d 1 d 2 d 3 cs 1 cs 0 v do interrupt out 1 2 3 4 5 6 7 8 9 18 17 16 14 13 12 11 10 ale 15 rd v ss xt xt wr a 1 a 0 a 2 a 3 d 0 d 1 d 2 d 3 cs 1 cs 0 v do 124 223 322 421 5 20 6 718 817 916 10 15 11 14 12 13 19 periodic out alarm out ale 30sec. adj 68/80 (e) rd v ss xt xt (nc) stop/start 1hz wr (r/ w ) cs 0 a 0 a 1 a 2 a 3 d 1 d 2 d 3 cs 1 1 219 3 20 18 417 516 615 714 813 912 10 11 interrupt out (nc) ale a 0 cs 0 a 1 a 2 a 3 rd v ss xt xt (nc) wr cs 1 d 0 d 1 d 2 d 3 v do 1 219 3 20 18 417 516 615 714 813 912 10 11 interrupt out (nc) ale a 0 cs 0 a 1 a 2 a 3 e v ss xt xt (nc) r/ w cs 1 d 0 d 1 d 2 d 3 v do 12 13 11 14 10 15 916 817 718 619 520 421 322 223 124 periodic out alarm out ale cs 0 a 0 a 1 30sec. adj a 2 a 3 68/80 (e) rd v ss xt xt (nc) stop/start 1hz cs 1 d 0 d 1 d 2 d 3 wr (r/ w ) v do v do d 0 pin configuration MSM6542-01rs 18-pin plastic dip (top view) msm6542-02rs 18-pin plastic dip (top view) msm6542-03rs 24-pin plastic dip (top view) MSM6542-01ms-k 20-pin plastic sop (top view) msm6542-02ms-k 20-pin plastic sop (top view) msm6542-03gs-vk 24-pin plastic sop (top view) nc : no connected (open)
? semiconductor MSM6542-01/02/03 70 functional block diagram (MSM6542-01, 02) 32.768khz xt xt osc reset stop less-than-second counter control counter d a t a i. f. d 3 d 2 d 1 d 0 a 3 a 2 a 1 a 0 cs 0 wr or r/ w rd or e (-1) (-2) r/w i f d.p. a d d r e s s i. f. d e c o d e r bank 1/0 ale cs 1 r-s i to c f a-s i to c e' r-s 1 r-s 10 r- mi 10 r-h 1 r-h 10 r-w r-d 1 r-d 10 r- mo 1 r- mo 10 r-y 1 r-y 10 comparator a-s 1 a-s 10 a-h 1 a-h 10 a-w a-d 1 a-d 10 a- mo 1 a- mo 10 a- mi 10 interrupt out c e' c c' a-en able c d' c f c e c d r- mi 1 a- mi 1 a l a r m o u t p e r i o d i c o u t
? semiconductor MSM6542-01/02/03 71 32.768khz xt xt osc reset stop 1hz less-than-second counter control counter d a t a i. f. r/w i f d.p. a d d r e s s i. f. d e c o d e r bank 1/0 d 3 d 2 d 1 d 0 a 3 a 2 a 1 a 0 cs 0 r/ w or wr e or rd 68/80 ale cs 1 30sec. adj stop/start r-s i to c f a-s i to c e' r-s 1 r-s 10 r- mi 10 r-h 1 r-h 10 r-w r-d 1 r-d 10 r- mo 1 r- mo 10 r-y 1 r-y 10 comparator a-s 1 a-s 10 a-h 1 a-h 10 a-w a-d 1 a-d 10 a- mo 1 a- mo 10 a- mi 10 p e r i o d i c o u t c e' c c' a-en able c d' c f c e c d alarm out periodic out r- mi 1 a- mi 1 a l a r m o u t functional block diagram (msm6542-03)
? semiconductor MSM6542-01/02/03 72 register table a d d r e s s a 3 a 2 a 1 a 0 register symbol d 3 d 2 d 1 d 0 register name bank 0 bank 1 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 r-s 1 r-s 10 r-mi 1 r-mi 10 r-h 1 r-h 10 r-d 1 r-d 10 r-mo 1 r-mo 10 r-y 1 r-y 10 r-w c d c e c f r-s 8 C r-mi 8 C r-h 8 C r-d 8 * r-mo 8 * r-y 8 r-y 80 C it/pls 2 irq flag 0 banki/0 r-s 4 r-s 40 r-mi 4 r-mi 40 r-h 4 r-pm/am r-d 4 * r-mo 4 * r-y 4 r-y 40 r-w 4 it/pls 1 rest stop r-s 2 r-s 20 r-mi 2 r-mi 20 r-h 2 r-h 20 r-d 2 r-d 20 r-mo 2 * r-y 2 r-y 20 r-w 2 mask 2 irq flag 2 30-s adjustment r-s 1 r-s 10 r-mi 1 r-mi 10 r-h 1 r-h 10 r-d 1 r-d 10 r-mo 1 r-mo 10 r-y 1 r-y 10 r-w 1 mask 1 irq flag 1 read flag real time one-second digit register real time ten-second digit register real time one-minute digit register real time ten-minute digit register real time one-hour digit register real time pm/am ten-hour digit register real time one-day digit register real time ten-day digit register real time one-month digit register real time ten-month digit register real time one-year digit register real time ten-year digit register real time day-of-week register control d register control e register control f register register symbol a-s 1 a-s 10 a-mi 1 a-mi 10 a-h 1 a-h 10 a-d 1 a-d 10 a-mo 1 a-mo 10 a-w a-enable c c' c d' c e' d 3 a-s 8 * a-mi 8 * a-h 8 * a-d 8 * a-mo 8 * * a-e 8 C C hd/sft d 2 a-s 4 a-s 40 a-mi 4 a-mi 40 a-h 4 a-pm/am a-d 4 * a-mo 4 * a-w 4 a-e 4 C cy 2 24/12 d 1 a-s 2 a-s 20 a-mi 2 a-mi 20 r-h 2 a-h 20 a-d 2 a-d 20 a-mo 2 * a-w 2 a-e 2 test 2 cy 1 cal d 0 a-s 1 a-s 10 a-mi 1 a-mi 10 a-h 1 a-h 10 a-d 1 a-d 10 a-mo 1 a-mo 10 a-w 1 a-e 1 test 1 cy 0 dp register name alarm one-second digit register alarm ten-second digit register alarm one-minute digit register alarm ten-minute digit register alarm one-hour digit register alarm pm/am ten-hour digit register alarm one-day digit register alarm ten-day digit register alarm one-month digit register alarm ten-month digit register alarm day-of-week register register to specify the alarm range control c register control d' register control e' register same as bank 0 since positive logic is used, the high level on a data bus corresponds to 1 in a register. when dp = 1, data can be written in the bank 1/0 and dp bits. wnen 0 is written in the dp bit, a delay is required until the bit is set at 0. read flag and irq.flag 0 are read-only flags. read flag is cleared after data is read from it. irq. flag 1 is cleared after data is read from it with it/pls 1 set at 1. when it/pls 1 is 0, only 0 can be written in irq. flag 1 and it cannot be cleared when it is read. similarly, irq. flag 2 is cleared after data is read from it with it/pls 2 set at 1. when it/pls 2 is 0, only 0 can be written in irq. flag 2 and it cannot be cleared when it is read. for the MSM6542-01/02, hd/sft is set internally at 0. data can be written in the c c' register but it is cleared when it is read. therefore, read data is always 0. when r-pm/am is 1, the time is p.m. when it is 0, the time is a.m. this is also true for a-pm/am. the contents of all registers are unpredictable when power is turned on from 0v to 5v. a hyphen in the table indicates that the bit is not present. when the bit is read, it always provides 0. when a bit marked an asterisk (*) in the table is used as part of a clock register or alarm register, it always provides 0 at r ead. when the bit is used as part of ram, however, it can be used for read and write. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. notes:
? semiconductor MSM6542-01/02/03 73 rating symbol condition value unit power supply voltage v dd ta = 25c C0.3 to 7 v input voltage v i ta = 25c C0.3 to v dd +0.3 v output voltage v o ta = 25c C0.3 to v dd +0.3 v storage temperature range t stg C C55 to +150 c absolute maximum ratings electrical characteristics rating symbol condition value unit power supply voltage v dd C 4.5 to 5.5 v clock power supply voltage v clk C 2.0 to 6 v crystal oscillator frequency ? (xt) C 32.768 khz operating temperature range t op C C40 to +85 c operation range note: the clock power supply voltage is required to assure operation of the crystal oscillator and clock. rating symbol condition max. applicable pin dc characteristics typ. min. high input voltage (1) low input voltage (2) input leakage (1) input leakage (2) high input current low input current high output voltage low output voltage (1) low output voltage (2) leakage current current consumption (1) current consumption (2) input capacitance (1) input capacitance (2) high input voltage (2) v ih1 v il2 i lk1 i lk2 i ih i il v oh v ol1 v ol2 i offlk i dd1 i dd2 c i1 c i2 v ih2 v 1 = v dd /0v v ih = 0.8 v dd v il = 0.2 v dd i oh = C400 a i ol = 2.5 ma i ol = 2.5 ma v i = v dd /0v oscillation at 32.768 khz v dd = 5v cs 1 0v v dd = 2v input oscillator frequency 1 mhz 2.2 C C1 C10 C100 20 2.4 C C C C C C C C C C C C C C C C C C C 3 5 C C 0.2 v dd 1 10 C20 100 C 0.4 0.4 10 30 5 C C C v a pf v a a low input voltage (1) v il1 0.8 v dd C C 0.8 cs 0 , a 0 ~a 3 , d 0 ~ d 3 rd (e), wr (r/ w ), ale, 30-s adj stop/start cs 1 , 68/80 cs 0 , ale, a 0 ~ a 3 , 68/80, rd (e), wr (r/ w ), cs1, 30-s adj d 0 ~ d 3 , stop/start stop/start d 0 ~ d 3 , 1hz interrupt periodic out alarm v dd input pins other than d o to d 3 d 0 to d 3 (v dd = 5v 10%, ta = -40 ~ +85c) ~ ~
? semiconductor MSM6542-01/02/03 74 cs 1 a 0 ~ a 3 cs 0 wr d 0 ~ d 3 (input) v ih2 t c1s t c1h v ih1 v il1 t rcv t aw t dh v ih1 v il1 v ihi = 2.2v v il1 = 0.8v 5 4 1 5 v ih2 = v dd v il2 = v dd v ih2 v ih1 v il1 v il1 v ih1 v ih1 v ih1 v il1 t ww t wa v ih1 v il1 t ds rating symbol condition max. unit C C C C C C C C (v dd = 5v 10%, ta = C40 to +85c (in the 80 mode for the MSM6542-01/03)) 80-xxx write mode (ale is always at v dd .) C C C C C C C C typ. 1000 1000 20 10 120 100 10 100 min. t c1s t c1h t aw t wa t ww t ds t dh t rcv switching characteristics cs 1 set-up time cs 1 hold time address stable before write address stabel after write write pulse width data set-up time data hold time rd / wr recovery time ns ns ns ns ns ns ns ns C C C C C C C C
? semiconductor MSM6542-01/02/03 75 cs 1 a 0 ~ a 3 cs 0 d 0 ~ d 3 (output) v ih2 t c1s t c1h v ih1 v il1 t rcv t dr v oh v ol v ih1 = 2.2v v il1 = 0.8v 5 4 1 5 v ih2 = v dd v il2 = v dd v ih2 v ih1 v il1 v il1 v ih1 v ih1 v oh v ol t ra t rd t ar "z" v oh = 2.2v v ol = 0.8v rd rating symbol condition max. unit C C C C cl = 150 pf C C (v dd = 5v 10%, ta = C40 to +85c (in the 80 mode for the MSM6542-01/03)) 80-xxx read mode (ale is always at v dd .) C C C C 120 45 C typ. C C C C C C C min. 1000 1000 20 20 C 10 100 t c1s t c1h t ar t ra t rd t dr t rcv cs 1 set-up time cs 1 hold time address stable before read address stable after read rd to data data hold rd / wr recovery time ns ns ns ns ns ns ns
? semiconductor MSM6542-01/02/03 76 cs 1 a 0 ~ a 3 cs 0 ale wr d 0 ~ d 3 (input) v ih2 t c1s t as t ah v ih1 v il1 t c1h t aw t alw t ww t wal t rcv t ds t dh v ih1 = 2.2v v il1 = 0.8v 5 4 5 1 v ih2 = v dd v il2 = v dd v ih2 v ih1 v il1 v ih1 v ih1 v il1 v ih1 v il1 v ih1 v il1 v ih1 v ih1 v il1 v ih1 v il1 rating symbol condition max. unit C C C C C C C C C C C (v dd = 5v 10%, ta = C40 to +85c (in the 80 mode for the MSM6542-01/03)) 80-xxx write mode (ale is used.) C C C C C C C C C C C typ. C C C C C C C C C C C min. 1000 25 25 40 10 120 20 100 10 1000 100 t c1s t as t ah t aw t alw t ww t wal t ds t dh t c1h t rcv cs 1 set-up time address set-up time address hold time ale pulse width ale before write write pulse width ale after write data set-up time data hold time cs 1 hold time rd / wr recovery time ns ns ns ns ns ns ns ns ns ns ns
? semiconductor MSM6542-01/02/03 77 cs 1 a 0 ~ a 3 cs 0 ale rd d 0 ~ d 3 (output) v ih2 t ah t as v ih1 v il1 t aw t rcv t alr t ral t rcv t rd t dr v oh v ol v ih1 = 2.2v v il1 = 0.8v 5 4 5 1 t c1s v ih2 = v dd v il2 = v dd v oh = 2.2v v ol = 0.8v v ih2 v ih1 v il1 t c1h v ih1 v ih1 v il1 v ih1 v il1 v ih1 v il1 v ih1 v il1 "z" rating symbol condition max. unit C C C C C C cl = 150 pf C C C (v dd = 5v 10%, ta = C40 to +85c (in the 80 mode for the MSM6542-01/03)) 80-xxx read mode (ale is used.) C C C C C C 120 45 C C typ. C C C C C C C C C C min. 1000 25 25 40 10 20 C 10 1000 100 t c1s t as t ah t aw t alr t ral t rd t dr t c1h t rcv cs 1 set-up time address set-up time address hold time ale pulse width ale before read ale after read rd to data data hold cs 1 hold time rd / wr recovery time ns ns ns ns ns ns ns ns ns ns
? semiconductor MSM6542-01/02/03 78 rating symbol condition max. unit C C C C C C C C cl = 150 pf C C (v dd = 5v 10%, ta = 0c to +70c (in the 86 mode for the msm6542-02/03)) 68-xxx C C C C C C C C 120 C C typ. C C C C C C C C C C C min. 1000 100 220 20 220 500 180 20 C 10 1000 t c1s t rwe t ehw t erw t elw t ec t ds t dhw t rd t dhr t c1h cs 1 set-up time r/ w address set-up time e 'h' pulse width r/ w address hold time e 'l' pulse width e cycle time data set-up time write data hold time e to data read data hold time cs 1 hold time ns ns ns ns ns ns ns ns ns ns ns v ih1 = 2.2v v il1 = 0.8v write mode cs 1 r/ w cs 0 a 0 ~ a 3 e d 0 to d 3 v ih2 t c1s t c1h v il1 v ih1 t rwe t ehw t erw t elw t ds t dhw input data t ec read mode output data t rd v oh 5 4 5 1 v ih2 = v dd v il2 = v dd v oh = 2.2v v ol = 0.8v v ih2 v il1 v il1 v ih1 v il1 v il1 v ih1 v ih1 v il1 v il1 v ih1 v il1 v ih1 v il1 v ih2 t c1s t c1h v ih1 v il1 t rwe t ehw t erw t elw v ih2 v ih1 v ih1 v il1 v ih1 v il1 v ih1 v ih1 v il1 v il1 t dhr v ol v oh v ol t ec cs 1 r/ w cs 0 a 0 ~ a 3 e d 0 to d 3
? semiconductor MSM6542-01/02/03 79 description of pins d 0 to d 3 (data bus pins 0 to 3) these input pins connected to the data bus of a microcomputer are used for the microcomputer to read and write registers. the interface uses the positive logic. when cs 0 is low, cs 1 is high, rd is low, and wr is high (for the 68-xxx system, cs 0 is low, cs 1 is high, r/ w is high, and e is high), these data bus pins are in the output mode. in the other cases, they are in the high impedance status. a 0 to a 3 (address bus pins 0 to 3) these input pins connected to the address bus of a microcomputer specify a register used by the microcomputer for read or write. the address data specified by these pins is used in conjunction with the input to the ale pin. ale (address latch enable) this input pin is for address and cs 0 . when the ale pin is high, the address bus data and cs 0 are read into the ic. when it is low, the address data and cs 0 read at ale = h are retained in the ic. cs 1 functions independently of the ale pin. when using an msc-48-, msc-51-, or 8085-based microcomputer having an ale output pin, connect this pin to the ale output pin of the microcomputer. when a four-bit microcomputer shares the four address bus pins, a 0 to a 3 , with another peripheral ic, the ale pin on this ic can be used to specify it. when the microcomputer has no ale output pin, connect the ale input pin on this ic to the v dd . wr [r/ w ] (write [read/ write ]) this input pin is connected to the wr pin for the 80-based cpu or the r/ w pin for the 68-based cpu. rd [e] (read [e]) this input pin is connected to the rd pin for the 80-based cpu or the e pin for the 68-based cpu. cs 0 , cs 1 (chip select pins 0 and 1) these input pins enable or disable input of ale, wr (r/ w ), and rd (e). when cs 0 is low and cs 1 is high, these inputs are enabled. in the other combinations, the ic unconditionally assumes that ale is low and wr and rd are high (for the 68-based cpu, e is low). however, cs 0 needs to operate in conjunction with ale and cs 1 operates independently of ale. connect cs 1 to the power supply voltage detection pin. for more information, see the descriptions in "usage" and "use of cs 1 ."
? semiconductor MSM6542-01/02/03 80 periodic out (only for the msm6542-03) this output pin is used for n-channel open drain. it outputs a single pulse or an interrupt request as a trigger each time a carry is generated from the clock counter. output from this pin is not disabled by cs 0 and cs 1 . alarm out (only for the msm6542-03) this output pin is used for n-channel open drain. it outputs a single pulse or an interrupt request each time the contents of the clock counter match the date and time for which an alarm is set. output from this pin is not disabled by cs 0 and cs 1 . interrupt out (only for the MSM6542-01/02) this output pin is n-channel open drain. it ors the signals from the periodic out and alarm out pins above. carry trigger periodic out v dd date and time matching trigger alarm out v dd interrupt out v dd carry trigger date and time matching trigger
? semiconductor MSM6542-01/02/03 81 xt and xt (x'tal osc) these pins are the connecting terminals to connect the capacitors and crystal oscillator at 32.768khz as shown below. v dd or gnd 5m w typ. 200k w typ. xt 32.768 khz c1 c2 xt msm6542 example (equivalent series resistance < 30 k w c 1 , c 2 = 15 to 30 pf) note: oscillation accuracy and allowable values of the equivalent series resistor for the crystal oscillator depend on the value of the capacitor used for oscillation. for selection of a crystal oscillator and the value of the capacitor needed for it, consult the crystal oscillator manufacturer. to supply external 32.768 khz clocks, enter cmos output or pulled-up ttl output to the xt pin and leave the xt pin open. v dd and v ss these are power supply pins. connect the v ss pin to ground and supply positive power to the v dd pin. the 1 hz, 30 sec adj, stop/start, and 68/80 pins described below are used only for the msm6542-03. 1 hz this output pin is used to confirm the oscillation frequency. it outputs 1-hz pluses at a duty cycle of 50%. this pin provides one-second output from the clock counter. therefore, it is cleared to a low when the rest bit is high or 30-second adjustment is performed. when stop function is performed, the output stops at whatever level the output is at that instant. this pin provides cmos output level, regardless of the level of the cs 1 pin. if a load is connected to this pin during standby operation, the battery will be quickly dissipated. =
? semiconductor MSM6542-01/02/03 82 30-sec adj (30-seconds adjustment) when this input pin goes high, 30-second adjustment is performed on the rising edge. when not used, connect to ground. stop/start this input pin can be used as an integrating clock. when the pin is high, clocking at frequencies lower than 4096 hz stops. when the pin goes low, clocking is resumed. the hd/sft bit of the c e ' register specifies whether the stop/start function is implemented by hardware or software. when not used, connect to ground. for more information, see the description of "c f register" and "c e ' register" in "explanation of registers." stop stop bit of the c f register hd/sft bit of the c e ' register stop/start start e q uivalent circuit of the stop/start p in inside of the msm6542 68/80 this input pin selects which cpu this ic is to be connected. to connect the ic to the 68-based cpu, leave the pin at v dd . to connect the ic to the 80-based cpu, leave the pin at the ground level.
? semiconductor MSM6542-01/02/03 83 explanation of registers registers r-s 1 , r-s 10 , r-mi 1 , r-mi 10 , r-h 1 , r-h 10 , r-d 1 , r-d 10 , r-mo 1 , r-mo 10 , r-y 1 , r-y 10 , r-w a) the letter r followed by a hyphen (-) in these register names indicate a realtime register. s 1 , s 10 , mi 1 , mi 10 , h 1 , h 10 , mo 1 , mo 10 , y 1 , y 10 , and w are abbreviations for second 1, second 10, minute 1, minute 10, hour 1, hour 10, day 1, day 10, month 1, month 10, year 1, year 10, and week. the value of each register is weighted in bcd. b) positive logic is used. for example, when (r-s 8 , r-s 4 , r-s 2 , r-s 1 ) is (1, 0, 0, 1), it indicates 9 seconds. c) an asterisk (*) in bank 0 in the realtime register table indicates the bit is automatically set at 0 even though the write data is 1, when the cal bit of the c e ' register is high. when the cal bit is low, registers r-d 1 , r-d 10 , r-mo 1 , r-mo 10 , r-y 1 , and r-y 10 are used as ram areas. the bits marked * in these ram areas can be used for write and read operations. for more information, see the description of "c e ' register" in "explanation of reg- isters." d) be sure not to set non-existent data in an non-ram area, that is, realtime registers. otherwise, a clock error may occur. e) r-pm/am, r-h 20 , and r-h 10 in the 12-hour clock mode, the possible hours are from 1 a.m. to 12 a.m. and from 1 p.m. to 12 p.m. when the bit is 1, it indicates p.m. when the bit is 0, it indicates a.m. in the 24- hour clock mode, the possible hours are from 0 o'clock to 23 o'clock. during write operation, the r-pm/am bit is ignored in the 24-hour clock mode and the r- h 20 bit in the 12-hour clock mode. during read operation, the r-pm/am bit is unconditionally set at 0 in the 24-hour clock mode and the r-h 20 bit in the 12-hour clock mode. f) r-y 1 and r-y 10 the ic described in this manual operates in gregorian years. when it operates in japanese calendar years (heisei), a leap year is also automatically determined. leap years are 1992, 1996, 2000, 2004, 2008, and so on.
? semiconductor MSM6542-01/02/03 84 r-w 4 day of the week 0 0 0 0 1 1 1 r-w 2 r-w 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 sun mon tue wed thu fri sat g) r-w the r -w bits counts from 0 to 6. an example of weighting is shown in the following table. days are not determined from dates. c d register (control d register) a) mask 1 (d 0 ) this bit controls periodic output for which a carry from the clock counter is used as a trigger. when the bit is 0, output is provided from the interrupt out pin for the MSM6542-01/ 02 or the periodic out pin for the msm6542-03. when the bit 1, output is disabled. the relationships between causes of periodic output and the status of the mask 1 bit are shown below. (for the MSM6542-01/02, data resulting from the oring of periodic output and alarm output is output to the interrupt out pin. for convenience, however, alarm output is ignored in the following description.)
? semiconductor MSM6542-01/02/03 85 i) in the periodic interrupt mode (when the it/pls 1 , bit is 1) *1 when dp = 1, the open state is not entered until a certain period passes after an interrupt is generated. (see the description of the c e register.) *2 however, when dp = 1, if the irq flag 1 bit is read out within 122 m s after an interrupt is generated, it is cleared after 122 m s from the generation of the interrupt. ii) in the periodic pulse output mode (when the it/pls 1 bit is 0.) the open status is entered when the irq flag 1 is read. (*1) no interrupt occurs because the mask 1 bit is 1. open low level interrupt timing "0" "0" "1" "1" interrupt out (-01, -02) periodic out (-03) mask 1 bit when the irq flag 1 is read during masking, irq flag 1 is not cleared. (*2) when 0 is written in the irq flag 1 bit, the open state is entered without having to wait for automatic restration the low level is not output because the mask 1 bit is 1. open low level output timing "0" "0" "1" mask 1 bit automatic restoration interrupt out (-01, -02) periodic out (-03) "1"
? semiconductor MSM6542-01/02/03 86 b) mask 2 (d 1 ) this bit controls the alarm output each time the contents of the clock counter match the date and time for which an alarm is set. when the bit is 0, an alarm is output from the interrupt out pin for the MSM6542-01/02 or the alarm out pin for the msm6542- 3. when the bit is 1, alarm output is disabled. the relationships between causes of alarm output and the status of the mask 2 bit are shown below. (for the MSM6542-01/02, data resulting from the or-ing of periodic output and alarm output is output to the interrupt out pin. for convenience, however, periodic output is ignored in the following description.) i) in the alarm interrupt mode (when the it/pls 2 bit is 1) the open status is entered when the irq flag 2 is read. (*1) a match for an alarm is not found because the mask 2 bit is 1. open low level match for an alarm "0" "0" "1" "1" interrupt out (-01, -02) alarm out (-03) mask 2 bit when the irq flag 2 is read during masking, irq flag 2 is not cleared. (*2) *1 when dp = 1, the open state is not entered until a certain period passes after an interrupt is generated. (see the description of the c e register.) *2 however, when dp = 1, if the irq flag 2 bit is read out within 122 m s after an interrupt is generated, it is cleared after 122 m s from the generation of the interrupt. ii) in the alarm pulse output mode (when the it/pls 2 bit is 0) when the irq flag 2 bit is set at 0, the open state is entered without having to wait for automatic restration the low level is not output because the mask 2 bit is 1. open low level match for an alarm "0" "0" "1" mask 2 bit automatic restoration interrupt out (-01, -02) alarm out (-03) "1"
? semiconductor MSM6542-01/02/03 87 c) it/pls 1 (d 2 ) (interrupt/pulse 1 ) this bit determines a mode for periodic output. when the bit is 1, a low-level interrupt request is output from the interrupt out pin for the MSM6542-01/02 or from the periodic out pin for the msm6542-3. when the bit is 0, a low-level pulse is output. in this case, the mask 1 bit is 0. the output periods of interrupt output and pulse output are determined by the setting of the c d ' register. d) it/pls 2 (d 3 ) (interrupt/pulse 2 ) this bit determines a mode for alarm output. when the bit is 1, a low-level alarm interrupt request is output from the interrupt out pin for the MSM6542-01/02 or from the alarm out pin for the msm6542-03. when the bit is 0, a low-level pulse is output. in this case, the mask 2 bit is 0. when the contents of the alarm register match those of the realtime counter within the range specified by the a-enable register, an output wave- form is provided. in the alarm pulse output mode, the low level of a pulse lasts for about 61 m s. c e register (control e register) a) irq flag 1 (d 0 ) (interrupt request flag 1 ) the status of this bit depends on the hardware output, low or open, from the periodic out pin for the msm6542-3 or interrupt out pin which uses carry as a trigger for the msm6542-1/2. when hardware output is low, the bit is set at 1. when it is open, the bit is set at 0. the irq flag 1 bit is mainly used to indicate that there is an interrupt request for the microcomputer. when the period set by the d 2 (cy 2 ), d 1 (cy 1 ), and d 0 (cy 0 ) bits of the c d ' register expires with the d 0 (mask 1 ) bit of the c d register set at 0, output from the in- terrupt out pin changes from open to low. at the same time, the irq flag 1 bit changes from 0 to 1. when the d 2 (it/pls 1 ) bit of the c d register is 1 (interrupt mode), the irq flag 1 bit remains at 1 (hardware output is low) until the bit is read. when the bit is read, it is cleared. however, when the irq flag 1 bit is read whithin about 122 m s of occurrence of an interrupt with the d 0 (dp) bit of the c e ' register set at 1, the irq flag 1 bit is not cleared immediately. it is cleared about 122 m s after the interrupt occurs. when the bit is read at least about 122 m s after an interrupt occurs, it is cleared immediately. in the interrupt mode, writing 0 in the irq flag 1 bit does not clear the bit. when another interrupt occurs with the bit set at 1, it is ignored. when the d 2 (it/pls 1 ) bit of the c d register is 0 (periodic pulse output mode), the irq flag 1 bit remains at 1 (hardware output is low) until 0 is written in the bit or the automatic restoration time determined by the period set by the d 2 (cy 2 ), d 1 (cy 1 ), and d 0 (cy 0 ) bits of the c d ' register expires. when the irq flag 1 bit is read in the periodic pulse output mode, it is not cleared.
? semiconductor MSM6542-01/02/03 88 i) in the interrupt mode (when the it/pls 1 bit is 1) (i-1) when dp is 0: the irq flag 1 bit is read interrupt timing "0" "1" "0" irq flag 1 irq flag 0 (i-2) when dp is 1: the irq flag 1 bit is read interrupt timing "0" "1" "0" irq flag 1 irq flag 0 122s 122s "1" note: when the irq flag 1 bit is read within the 122 m s interval with the mask 1 bit set at 1, it is not cleared. the irq flag 1 bit is cleared after the 122 m s interval ends. ii) in the periodic pulse output mode (when the it/pls 1 bit is 0) 0 is written in the irq flag 1 bit with dp set at 0 output timing "0" "1" "0" irq flag 2 irq flag 0 automatic restoration
? semiconductor MSM6542-01/02/03 89 b) irq flag 2 (d 1 ) (interrupt request flag 2 ) the status of this bit depends on the hardware output, low or open, from the alarm out pin for the msm6542-03 or interrupt out pin which uses a match with a set alarm time as a trigger for the MSM6542-01/02. when hardware output is low, the bit is set at 1. when it is open, the bit is set at 1. the irq flag 2 bit is mainly used to indicate that there is an alarm timer interrupt for the microcomputer. when the time set by alarm registers, a-s 1 to a-w, and the a-enable register expires with the d 1 (mask 2 ) bit of the c d register set at 0, hardware output changes from open to low. at the same time, the irq flag 2 bit changes from 0 to 1. when the d 3 (it/pls 2 ) bit of the c d register is 1 (alarm interrupt mode), the irq flag 2 bit remains at 1 (hardware output is low) until the bit is read. when the bit is read, it is cleared. however, when the irq flag 2 bit is read within about 122 m s of occurrence of an alarm interrupt with the d 0 (dp) bit of the c e ' register set at 1, the irq flag 2 bit is not cleared immediately. it is cleared about 122 m s after the interrupt occurs. when the bit is read at least about 122 m s after an interrupt occurs, it is cleared immediately. in the alarm interrupt mode, writing 0 in the irq flag 2 bit does not clear the bit. when another interrupt occurs with the bit set at 1, it is ignored. when the d 3 (it/pls 2 ) bit of the c d register is 0 (alarm pulse output mode), the irq flag 2 bit remains at 1 (hardware output is low) until 0 is written in the bit or automatic restoration is performed about 61 m s later. when the irq flag 2 bit is read in the alarm pulse output mode, it is not cleared. i) in the alarm interrupt mode (when the it/pls 2 bit is 1) (i-1) when dp is 0: (i-2) when dp is 1: the irq flag 2 bit is read alarm interrupt timing "0" "1" "0" irq flag 2 irq flag 0 the irq flag 2 bit is read alarm interrupt timing "0" "1" "0" irq flag 2 irq flag 0 122s 122s "1" note: when the irq flag 2 bit is read within the 122 m s interval with the mask 1 bit set at 1, it is not cleared. the irq flag 2 bit is cleared after the 122 m s interval ends.
? semiconductor MSM6542-01/02/03 90 ii) in the alarm pulse output mode (when the it/pls 2 bit is 0) 0 is written in the irq flag 2 bit with dp set at 0 output timing "0" "1" "0" irq flag 2 irq flag 0 automatic restoration 61s c) rest (d 2 ) (reset) this bit resets the less-than-second counter. while the bit is 1, the counter is being reset. when 0 is written in the bit, reset is canceled. when cs 1 goes low, the rest bit is automatically set at 0. when 1 is written in the bit, the test 1 and test 2 bits of the c c ' register are also set at 0. d) irq flag 0 (d 3 ) (interrupt request flag 0 ) this bit indicates whether the extended time zone for interrupt output is in progress when the dp is 1. the bit is set at 1 when: (1) the d 2 (it/pls 1 ) bit of the c d register is 1 (periodic interrupt mode) or the d 3 (it/pls 2 ) bit of the c d registe is 1 (alarm interrupt mode), (2) the d 0 (dp) bit of the c e ' register is 1 (data protect mode), and (3) 122 m s (extended time zone) do not elapse after a periodic interrupt or an alarm interrupt occurs. when 122 m s elapse after occurrence of such an interrupt, the bit is automatically set at 0. the bit is not cleared when it is read. also, data cannot be written in the bit. c f register (control f register) a) read flag (d 0 ) this bit indicates a one-second carry. it is used to read time data. when the read flag bit is read, it is reset at 0. the status lasts until the less-than-second realtime counter generates a carry to the one-second counter. when a carry to the one-second realtime counter is generated, the read flag bit is set at 1. the status lasts until the bit is read. when a carry to the one-second realtime counter is generated with the read flag bit set at 1, the bit remains unchanged, i.e., at 1. the read flag bit is also set at 1 when 30-s adjustment is performed by software or hardware. the status last until the bit is read. for the usage of the read flag bit, see "reading registers" in reference flowcharts.
? semiconductor MSM6542-01/02/03 91 b) 30-s adj (d 1 ) (30-s adjustment) when 1 is written in this bit, software makes a 30-s adjustment. for 125 m s after this writing, registers r-s 1 to r-w (at addresses 0 to c in bank 0 in the register table) cannot be read or written due to limitations to the inside of the ic. when the cal bit of the c e ' register is 0, however, registers r-d 1 to r-y 10 (at addresses 6 to b in bank 0) which can be used as ram are as can be read or written during 30-s adjustment. the bit remains at 1 for up to 250 m s after 1 is written in the bit. then, the bit is automatically reset at 0. confirm that the bit is automatically reset at 0 before manipulating registers r-s 1 to r-y 10 and r-w (when cal is 0, r-s 1 to r-h 10 and r-w). the 30-s adj bit is also set at 1 when hardware makes a 30-s adjustment. in this case too, confirm that the bit is automatically reset at 0 before manipulating registers r-s 1 to r-y 10 and r-w (when cal is 0, r-s 1 to r-h 10 and r-w). when the 30-s adj bit is set at 1, the d 0 (read flag) of the bit c f register is also set at 1. c) stop (d 2 ) this bit is used for the integrating clock operated by software. when the bit is set at 1, clocking at 4096 hz and lower stops. when the bit is set at 0, clocking is resumed. for the msm6542-3, the hd/sft bit of the c e ' register can be used to select hardware or software to implement the stop/restart function. d) bank 1/0 (d 3 ) when this bit is set at 1, bank 1 is selected. when it is set at 0, bank 0 is selected. the bit can be set even in the data protect mode. registers a-s 1 , a-s 10 , a-mi 1 , a-mi 10 , a-h 1 , a-h 10 , a-d 1 , a-d 10 , a-mo 1 , a-mo 10 , a-w a) the letter a followed by a hyphen (-) in these register names indicate an alarm register. s 1 , s 10 , mi 1 , mi 10 , h 1 , h 10 , mo 1 , mo 10 , and w are abbreviations or second 1 , second 10 , minute 1 , minute 10 , hour 1 , hour 10 , day 1 , day 10 , month 1 , month 10 , and week. the value of each register is weighted in bcd. b) the positive logic is used. for example, when (a-s 8 , a-s 4 , a-s 2 , a-s 1 ) is (1, 0, 0, 1), it indicates 9 seconds. c) an asterisk (*) in the alarm register table indicates the bit automatically set at 0 even though the write data is 1. this is true when the alarm register is in the alarm setting range set by the a-enable register. the registers outside the alarm setting range set by the a-enable register are used as ram areas. the bits marked * in these ram areas can be used for write and read operations. for more information, see the descriptions of "a-enable." d) be sure not to set non-existing data in alarm registers in the alarm setting range. otherwise, an alarm may not be generated.
? semiconductor MSM6542-01/02/03 92 e) a-pm/am, a-h 20 , and a-h 10 in the 12-hour clock mode, the possible hours are from 1 a.m. to 12 a.m. and from 1 p.m. to 12 p.m. when the bit is 1, it indicates p.m. when the bit is 0, it indicates a.m. in the 24- hour clock mode, the possible hours are from 0 o'clock to 23 o'clock. in the 12-hour clock mode, the a-h 20 bit is write-enabled. when 1 is written in it, an alarm indicating an impossible time is generated. this is also true for the other registers: when an impossible alarm time is set, no alarm is generated. in the 24-hour clock mode, the a-pm/am bit is read- and write-enabled but its status is assumed to be always the same as that of the r-pm/am bit. f) a-w the a-w bits use the numbers from 0 to 6. weight these bits in the same way as for r-w. g) the alarm registers are not incremented or decremented a-enable register (alarm enable) this register sets a comparison range for the real time counter and alarm registers. the alarm registers outside the comparison range can be used as four-bit ram areas. (the bits marked an asterisk (*) in the register table can be used for write and read operations. when dp is 1, however, write operation is not possible.) the following table shows the relationships between the status of the a-enable register bits and alarm comparison ranges.
? semiconductor MSM6542-01/02/03 93 ae8 alarm comparlson range 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 none a ~ s 1 a-s 1 ~ a-s 10 a-s 1 ~ a-mi 1 a-s 1 ~ a-mi 10 a-s 1 ~ a-h 1 a-s 1 ~ a-h 10 a-s 1 ~ a-d 1 a-s 1 ~ a-d 10 a-s 1 ~ a-mo 1 a-s 1 ~ a-mo 10 a-s 1 ~ a-h 10, a-w a-s 1 ~ a-d 1, a-w a-s 1 ~ a-d 10, a-w a-s 1 ~ a-mo 1, a-w a-s 1 ~ a-mo 10, a-w ae4 ae2 ae1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 c c register (control c' register) this register is a test register. the user can use it when both the test 1 (d 0 ) and test 2 (d 1 ) bits of the register are 0. when either or both test bits are 1, oki's test functions are enabled, making the execution results of user's functions unpredictable. when the register is read, it is automatically cleared. the read value is always 0. when 1 is written in the rest (d 2 ) bit of the c e register, the c c ' register is automatically set at 0. c d register (control d' register) this register sets an interrupt period when the it/pls 1 (d 2 ) bit of the c d register is 1 and a pulse output period when the bit is 0. the following table shows the relationships between the status of the c d ' register bits and the length of periods.
? semiconductor MSM6542-01/02/03 94 cy 0 duty cycle of the low level when it/pls 1 = 0 0 0 0 0 1 1 1 1 cy 2 cy 1 1/2 1/2 1/2 1/2 1/2 1/8192 1/491520 1/4915200 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 period 1/1024 s 1/128 s 1/64 s 1/16 s 1/2 s 1 s 1 min 10 min c e register (control e' register) a) dp (d 0 ) (data protect bit) this bit has the following two functions: i) restricts write operation to the ic. ii) prolongs the resetting of the irq flag 1 bit when the bit is read within 122 m s of occurrence of a periodic alarm in the periodic interrupt mode. also prolongs the resetting the irq flag 2 bit in the same way in the alarm interrupt mode. i) restriction of write operation when the dp bit is 0, normal write operation is enabled. when the bit is 1, however, the ic is write-protected except the bank 1/0 (d 3 ) bit of the c f register for which write operation is always allowed. the dp bit is designed to protect the registers from extenal noise, particularly erroneous write signal noise which is generated when the standby power supply voltage is switched to the system power supply voltage or vice versa. after the necessary data is written, it is recommended that the dp bit be set at 1 if only read operation is performed. ii) prolongation of reset of the irq flag bits when the it/pls 1 (d 2 ) bit of the c d register is 1 (periodic interrupt mode) with the dp bit set at 0, reading the c e register clears the irq flag 1 bit. this is also true for the it/pls 2 (d 3 ) bit when it is 1 (alarm interrupt mode): reading c e register clears the irq flag 2 bit. when the irq flag 1 bit is read within about 122 m s of occurrence of an interrupt with the it/pls 1 (d 2 ) bit of the c d register set at 1 (periodic interrupt mode), the irq flag 1 bit is not cleared immediately. similarly, the irq flag 2 bit is not cleared immediately when the it/pls 2 (d 3 ) bit is 1 (alarm interrupt mode). these irq flag bits are cleared about 122 m s after an interrupt occurs. when these bits are read at least about 122 m s after an interrupt occurs, they are cleared immediately. for more information, see the description of "c e register."
? semiconductor MSM6542-01/02/03 95 when an irq flag bits are read mistakenly due to external noise, particularly erroneous read signal noise which is generated when the standby power supply voltage is switched to the system power supply voltage or vice versa, therefore, the irq flag bits are not cleared immediately but read at the correct times. when 1 is written in the dp bit, the bit is immediately set at 1 except the following two cases. (i) the cs 1 bit is low. (ii) for 62 m s immediately after the dp bit changes from 1 to 0. writing 0 in the dp bit, that is, canceling data protection is allowed only when: (i) zero is written in the dp bit more than 2 ms after cs 1 changes from low to high. (ii) the cs 1 bit is high 11 ms after 0 is written in the dp bit. b) cal (d 1 ) (calendar) this bit specifies a range in which the realtime counter is incremented. when the bit is 1, the r-s 1 to r-y 10 and r-w register can be incremented. when the bit is 0, the r-s 1 to r-h 10 and r-w registers can be incremented. with the cal bit set at 1, r-d 1 to r-y 10 are used as realtime registers. therefore, setting an impossible time in these registers causes an error. for the bits marked an asterisk (*) of the r-d 10 and r-mo 10 registers in the register table, when 1 is written, 0 is automatically set. the alarm comparison range is specified by the a-enable register. when the cal bit is 0, the r-d 1 to r-y 10 registers are not incremented. they can be used as static ram, enabling arbitrary values to be set. the bits marked an asterisk (*) of the r-d 10 and r-mo 10 registers in the register table can be subject to both write and read operations. the alarm comparison range is specified by the a-enable register. however, the r-d 1 to r-y 10 registers are assumed to always provide a match. when these registers are used as static ram, they cannot be rewritten when the dp bit is 1. cs 1 data protection can be canceled because cs 1 is high 0 is written in the dpbit dpbit 1 is written in the dpbit 11ms 1 written in the dpbit in this period is ignored 62s
? semiconductor MSM6542-01/02/03 96 c) 24/12 (d 2 ) (24-hour clock/12-hour clock) this bit selects a 24-hour clock or 12-hour clock mode. when the bit is 1, the 24-hour clock mode without pm/am specification is enabled. when the bit is 0, the 12-hour clock mode with pm or am specified is enabled. when the 24/12 bit is rewritten, data in the r-h 1 register and higher will be destroyed. the data needs to be written again. d) hd/sft (d 3 ) (hardware/software)(this bit applicable only to the msm6542-03) this bit determines which mode, hardware or software, is enabled to validate the stop/start function. when the bit is 1, hardware enables the stop/start function (pin 20). when the bit is 0, software enables the stop/start function (d 2 of the c f register) the stop/start function by hardware and that by software cannot be used at the same time. for the MSM6542-01/02, the stop/start function by software is always enabled due to an internal setting on the ic. however, the hd/sft bit can be read or written to freely regardless of this setting, enabling the bit to be used as a memo bit.
? semiconductor MSM6542-01/02/03 97 usage pattern layout the oscillation stage of the 32.768 khz oscillator circuit is at a high impedance to achieve very low power dissipation. in addition, since sine waves are produced at as low as 32.768 khz, oscillation waves stay near the threshold for a longer time. for this reason, countermeasures must be taken against power supply noise and external noise from the viewpoint of an analog ic. countermeasures against power supply noise insert a 4.7 m f tantalum capacitor and 0.01 m f ceramic capacitor as close to the ic as possible. when another ic (for example, backup ram) is used in the battery-backed circuit, also insert a by pass capacitor in that ic. countermeasures against external noise place the crystal for the oscillator circuit and the capacitors as close to the ic as possible. do not route other signal lines in the oscillator circuit regardless of whether the oscillator circuit is placed on the front or back of the pc board. sufficiently separate the xt and xt signal lines from the other signal lines regardless of whether these signal lines are running on the fron or back of the pc board (see a.. and b.. of the figure below). for the MSM6542-01/02 for the msm6542-03 v dd xt xt a b 2 1 1 3 7.5 mm 3 5 mm 2 from v ss pin pass capacitor v dd xt xt a b 2 1 1 3 0.3 inch 3 0.2 inch 2 from pin 12 (v ss ) nc enclose the v dd line oscillation section v dd xt xt a b 2 1 from v ss pin bypass capacitor v dd xt xt a b 2 1 from pin 12 (v ss ) nc bypass capacitor
? semiconductor MSM6542-01/02/03 98 sample connection to a microcomputer various microcomputers are upgraded day by day. updated versions of this data sheet may not be capable of keeping pace with this progress. check the matching of switching characteristics in advance. msc51 msm6542 decoder d 3 d 2 d 1 d 0 a 3 a 2 a 1 a 0 cs 0 rd wr rd wr ale 3 2 1 0 port port 4 ~ 7 ale mc6809 msm6542 decode r d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 a 3 a 2 a 1 a 0 a 3 a 2 a 1 a 0 cs 0 ale v dd a 4 ~ a 15 e r/ w e r/ w [mcs51] [mc6809] decoder d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 a 3 a 2 a 1 a 0 a 3 a 2 a 1 a 0 cs 0 rd wr v dd g1 g2 a 4 ~ a 15 iorq or mreq rd wr ale [for the z80] note: select either iorq or mreq so that the z80 switching characteristics determined by the crystal oscillator for the z80 match those of the ic described in this data sheet.
? semiconductor MSM6542-01/02/03 99 sample peripheral circuits before using sample peripheral circuits shown below, check them against the user's system. power supply circuit (place a bypass capacitor as close to the ic as possible.) [when power is supplied from the +5v power supply] +5.1v a495 v ce (sat) = 0.1v 4.7f tantalum capacitor v dd v ss msm6542 + + 0.01 ceramic capacitor + 22 r* 10k 51k 10k c372 1.2 x 3 = 3.6v cadmium battery when the power supply is turned off, inverse current flows temporarily from the collector of the a495 transistor to the emitter. to deal with this problem, use a large value capacitance. r*: for less than charge current limit is1588 v = 0.69v f +5.7v alternative circuit r 4.7 + 0.01 v dd gnd msm6542 tantalum capacitor ceramic capacitor lithium battery r: limit resistance to conform to the ul standard. the value depends on the nominal capacity of the battery used. consult the battery manufacture. c372 v f = 0.69v or schottky diode main power supply (5v) main power supply (5v) one-chip voltage detector ic v dd v ss cs 1 msm6542 this circuit detects a rough voltage level. it is suitable for a system for which the dp bit is set at 1. v dd v ss cs 1 msm6542 sample main power supply monitor circuit
? semiconductor MSM6542-01/02/03 100 oscillation frequency adjustment [for the MSM6542-01/02] 18 17 16 3 2 1 interrupt out v dd xt xt screwdriver used for adjustment eye v dd 3.3 ~ 10k frequency counter turn on power c f (1, 0, 0, 0) read c register c' c e' (x, x, x, 0) read c e' register dp = 0 ? n y *1 c d' (0, cy 2 , cy 1 , cy 0 ) c f (0, 0, 0, 0) c e (0, 0, 0, 0) c d (0, 1, 1, 0) read c e register *2 to the next p a g e banks are switched ? x for (d 3 , d 2 , d 1 , d 0 ) is a don't care bit dummy read to clear the test bits procedure for canceling data protection set a frequency of the signal to be output from pin 1. examples 64 hz: (0 0 1 0) (duty cycle: 1/2) 1 hz: (0 1 0 1) (duty cycle: 1/8192) banks are switched. the stop bit is cleared. the reset bit is cleared preparation for a carry (oscillation). when an alarm occurs, a carry is inhibited. dummy read to clear the irq flag bit 1
? semiconductor MSM6542-01/02/03 101 frequency counter eye frequency adjustment c d (0, 0, 1, 0) read c e register *3 irq flag = 1 ? 1 a carry (oscillation) is checked output of a signal at the frequency set by c d' is command through pin 1. n y *1 to cancel data protection, oscillation must be in progress. it takes about 13 ms (2 ms during which the writing of dp ? 0 is inhibit in the rising of cs 1 plus 11 ms required until dp = 0 is executed.) this loop includes a wait time before oscillation starts. usually, the loop takes 0.5 to 2 seconds. when the power is turned on, the value of the dp bit is unpredictable. when the value is 0 incidentally, the loop does not return. *2, 3 the irq flag 1 is cleared at the step marked *2. if irq flag 1 = 1 is detected in the loop marked *3, therefore, it means that original oscillation is divided. other notes possible causes why the loop marked *1 or *3 becomes endless yes ? ? incorrect programming ? the frequency counter is not adjusted. observe the waveform at pin 1 on an oscilloscope. oscillation waveform at xt no ? ? oscillation is impeded by a leak due to a dirty pc board. clean the pc board. ? the capacitance of the capacitor for oscillation is inadequate. consult the crystal manufacturer. ? defective crystal oscillator or ic. re- place it.
? semiconductor MSM6542-01/02/03 102 possible causes when the loop marked *1 or *3 takes a long time (2 or 3 seconds or more) ? oscillation is impeded by a leak due to a dirty pc board. clean the pc board. ? the capacitance of the capacitor for oscillation is inadequate. consult the crystal manufactuer. possible causes why the frequency counter is not stable. ? the frequency counter is not adjusted. observe the waveform at pin 1 on an oscilloscope. ? the pattern layout is incorrect. see the description of "pattern layout." insert a bypass capacitor having a capacitance of at least 1 m f between the v dd and v ss pins.
? semiconductor MSM6542-01/02/03 103 for the msm6542-03 for the notes for "1, "2 and "3 and other notes are same as for the MSM6542-01/02. frequency adjustment (1hz) banks are switched read c f register read c f register dummy read to clear the test bits procedure for canceling data protection banks are switched. the stop bit is cleared the reset bit is cleared dummy read to clear the irq flag bits c f (1, 0, 0, 0) read c e' register c e' (x, x, x, 0) c f (0, 0, 0, 0) c e (0, 0, 0, 0) *2 *1 n frequency counter frequency counter screwdriver used for adjustment eye eye y y *3 read flag=1? 22 23 24 21 dp =0? 2 13 xt xt v dd turn on power 1hz 17 read c c' register n
? semiconductor MSM6542-01/02/03 104 use of cs 1 v ih and v il of cs 1 has the following three functions: 1. validate the interface with the microcomputer when 5v power is used. 2. inhibit use of the control bus, data bus, and address bus and prevent through-current specific to cmos input in the standby mode. 3. protect register data of the ic when the standby mode is entered or exited. to implement these functions: 1. to validate the interface with the microcomputer when 5v power is used, input must be at least 4/5 v dd . 2. when the mode is switched to the standby mode, input must be 1/5 v dd or less to inhibit use of the buses. in the standby mode, input must be nearly 0v to prevent through-current. 3. when the standby mode is entered or exited, the main power and cs 1 must conform the following timing charts: note: in the standby mode, the operating power supply voltage is from 4v to 2v (minimum value). clocking is performed but the interface to the outside of the ic is not assured. when a system is implemented with dp = 0: exiting from the standby mode 4 ~ 6v 4 ~ 4.5v* 1s(min) 1s(min) main power supply (5v) 4 ~ 4.5v* cs 1 switching to the standby mode power off 4 5 v dd 1 5 v dd (v dd for the ic described in this data sheet is 2 to 6 v.) during the period, cs 0 of the ic is high or wr is not generated. 4 to 4.5v* are measures of the minimum 5-v main power supply voltage at which the cpu does not assure correct program operations. this is also the for the followin g timin g chart: the purpose is to maintain data in static ram in the standby mode. 0v on and after this period, the interface through the ic is possible
? semiconductor MSM6542-01/02/03 105 when a system is implemented with dp = 1: switching to the standby mode existing from the standby mode power off * 2 2 v or more 2 v or more 4 ~ 6v 4 ~ 4.5v main power supply (4 ~ 4.5v) cs 1 4 5 v dd 1 5 v dd a *1 0v b *1, *2: ? the duration in this interval must be 8.7 ms or less. ? through current at the input stage (a 0 ~ a 3 , d 0 ~ d 3 , control inputs) caused by intermediate voltage input level and bus charge current cuaused by not programmed read out operation of cpu will dissipate power source. therefore, it is recommended that the voltage for monitoring the power supply of the cs1 control system be higher than the main power supply/battery switching voltage so that battery backup is enabled only in the interval from a .. to b .. .
? semiconductor MSM6542-01/02/03 106 reference flowcharts in the following flowcharts, description of bank switching is omitted. [power on sequence when dp is 0] apply 5v read c register c' n y *1 *2 c e' register dp 0 idling for at least 11ms dp = 0 read c e' register what status before 5v is applied? *3 are contents of individual register correct does operator determine that the current time is correct c e register rest 1 idling for 123 s set individual registers check contents of individual register c e register rest 0 standby unclear no yes v dd = 0v yes *4 *5 no (cs 1 ) the test bit is cleared. time until the dp bit becomes 0 under assumption that oscil- lation is in progress. when the voltage before 5v is applied is 0v, this loop takes the time equal to the one re- quired to start oscillation. usually, it takes 0.5 to 2 s. the contents of r-s, to r-y 10 and r-w must be possible values and the values of the other registers must be as expected. wait time until a carry which may be generated is com- pleted. *1 *2 *3 *4 *5
? semiconductor MSM6542-01/02/03 107 [power on sequence when dp is 1] apply 5v read c c' register dp = 1 ? c e' register dp 0 c e' register dp 1 idling for at least 11ms read c ' register e read c e' register check contents of individual registers dp = 0 ? c e' register dp 1 standby unclear what status before 5v is applied? c e' register dp 1 are connents of individual register correct? does operator determine that the current time is is correct? idling fore at least 11ms check that dp is 0 idling for 125 s set individual registers c e register rest 0 check that dp is 1 n y *3 n *5 y no *3 yes yes no *4 *4 (cs 1 ) v dd = 0v *1 c e register rest 1 c e' register dp 1 *1 the test bit is cleared. *2 it takes 9 to 11 ms from when 0 is written in the dp bit to when it is set at 0 in the ic. if 0 is written unintentionally in the dp bit during application of 5v power, it may be set at 0. to prevent this, first set the dp bit at 0 then at 1. when the voltage before 5v is applied is 0v, this loop takes the time equal to the one required to start oscillation. usually, it takes 0.5 to 2 s. *3 time until the dp bit becomes 0 under assumption that os- cillation is in progress. *4 the contents of r-s1, to r- y10 and r-w must be pos- sible values and the values of the other registers must be as expected. *5 wait time until a carry, which may be generated, is com- pleted.
? semiconductor MSM6542-01/02/03 108 [temporarily canceling dp = 1 in a system for which dp is set at 1] idling read c ' register e dp = 0? rewrite individual registers idling dp = 1 * 2 * 3 * 1 * 2 n * 3 n y dp 0 dp 1 or read c e' register idling for at least 11ms check that dp is 0 rewrite individual registers idling * 1 dp 1 dp 0 y *1 time until the dp bit becomes 0 under assumption that oscillation is in progress. *2 see "rewriting individual register." *3 writing 1 in it is inhibited for 62 m s after the dp bit is set at 0. this idling is provided to make the dp bit wait to be set at 1. *1 processing by other ic or wait time to prevent unneces- sary readouts which occur frequently. a measure is 1 ms. *2 see "rewriting individual register." *3 wait time to prevent unnecessary readouts which occur frequently. a measrue is 10 m s.
? semiconductor MSM6542-010/2/03 109 [rewriting individual registers] when bits other than the bank 1/0 and dp bits are rewritten, the dp bit must be 0. (a) r-s 1 to r-y 10 and r-w (for the msm6542-3, 30s adjustment must not be performed through pin 6 during rewriting.) read c f register idling idling for 126 s rf = 1 ? a carry is found * 1 * 3 * 6 n y * 5 * 2 * 1 * 2 rest 0 alternatively, stop 1 rewrite r-s 1 to r-y 10 and r-w rewrite r-s 1 to r-y 10 and r-w c e register rest 1 alternatively, c f register stop 1 or idling for 65 s read c f register * 4 *1 dummy read to clear the read flag (rf) bit. *2 processing by other ic or wait time to prevent unnecessary readouts which occur frequently. a measure is 50 ms. *3, *4, *5 to assure that rewriting is com- pleted before the next carry is generated, the time required for the step marked *5 must not be longer than 1 s minus time re- quired for steps marked *2 to *4. *6 time required for a carry pulse to complete operation *1 wait time until a carry which may be generated before 1 is written in the rest (or stop) bit is com- pleted *2 when 1 is written in the rest bit, clocking is delayed for the dura- tion during which the less-than- second counter is cleared and clocking is stopped until 0 is writ- ten in the rest bit. when 1 is written in the stop bit, clocking is delayed for the duration during which clocking is stopped initial 0 is written in the stop bit.
? semiconductor MSM6542-01/02/03 110 (b) ? r-d 1 to r-y 10 when the cal bit is 0 ?c d , rest bit of c e , and c f (excluding the bank 1/0 bit) ? a-s 1 to a-m 10 and a-w ? a-enable and c d ' ?c e ' (excluding the dp bit) there is no restriction other than by the dp bit. (c) bank 1/0 this bit can be rewritten freely even when the dp bit is 1. (d) 30-s adj method 1 c f register 30-s adj 1 idling is 30-s adj bit 0 ? read c f register y * n *at least about 100 m s method 2 idling for 255 s c f register 30-s adj 1 * * maximum time required for 30sec adjustment under assumption that oscillation is in progress (e) dp dp 1: rewriting is possible 62 m s after the dp bit changes to 0. dp 0: see "temporarily canceling dp = 1 is a system for which dp is set at 1."
? semiconductor MSM6542-010/2/03 111 [reading individual registers] (a) ordingary registers any registers can be read freely. however, the contents of the following bits change after they are read. ?c e register irq flag 1 : when 1 is read from this bit with it/pls 1 set at 1, the bit is cleared after read. for the timing when the bit is cleared, see the description of the irq flag 1 bit of the c e register. irq flag 2 : when 1 is read from this bit with it/pls 2 set at 1, the bit is cleared after read. for the timing when the bit is cleared, see the description of the irq flag 2 bit of the c e register. read flag : when 1 is read from this bit, the bit is cleared after read. test 1 , test 2 : these bits are reset immediately when they are read. therefore, 0 is always read from these bits. (b) reding time method 1 (unscheduled reading) n rf = 0 read c f register read clock registers * 2 * 1 * 3 y there is no carry while the clock registers are being read. idling for 3 s read c f register *1 dummy read to clear the read flag (rf) bit *2 time required to increment the ripple counter *3 loop to retry read because of a carry generated in the one-second digit counter during clock register reading
? semiconductor MSM6542-01/02/03 112 method 2 (periodic readout) c d' (0, d 2 , d 1 , d 0 ) * 2 it/pls 1 1 mask 1 0 read c e register * 3 * 4 idling the cpu detects an interrupt read c e register irq flag 1 = 1 y when dp is 1 when dp is 0 idling for at least 3 s inhibit cpu from accepting interrupts read clock registers read clock registers idling for at least 3 s * 5 * 5 idling * 6 allow cpu to accept interrupts other causes * 7 * 8 n * 1 interrupt handling routine *5 time required to increment the ripple counter *6, *7 the length of the time must be 122 m s or more because interrupt output is delayed 122 m s due to dp = 1. the idling market *6 is provided for this adjustment. *8 to assure that readout is completed before the next carry is generated, the time required for these steps must not be longer than the minimum set time unit. *1 only for initial setting at power on *2 the values of d2, d1, and d0 depend on the required minimum time unit as follows: d2 d1 d0 when up to 1 s is required 1 0 1 when up to 1 min is required 1 1 0 when up to 10 min are required 1 1 1 *3 dummy read to clear the irq flag 1 bit *4 122 m s when the dp bit is 1,0 m s when the dp bit is 0
? semiconductor MSM6542-010/2/03 113 method 3 (for each second carry) (a) setting (d2, d1, d0) at (1, 0, 1) in method 2 (periodical readout) described above (b) polling read c f register rf = 1 ? idling n * 1 * 3 idling for 3 s read clock registers read c f register rf = 0 ? discard read data use read data n y * 2 y *1 processing by other ic or wait time to prevent unnecessary readouts which occur frequently. a measure is 50 ms. *2 time required to increment the ripple counter *3 loop to retry read because of a carry generated during clock register reading
? semiconductor MSM6542-01/02/03 114 [setting for periodic pulse output] perform the following setting with the dp bit set at 0. the set values are independent of the setting of the dp bit. (a) periodic pulse output (*1) (b) alarm pulse output (*1) * 2 * 3 c d register it/pls 1 0 mask 1 1 c e register irq 0 flag 1 set c d' register (*, cy 2 , cy 1 cy 0 ) c d register it/pls 1 0 mask 1 0 c e register irq 0 flag idling for 185 s * 2 * 3 * 4 set a-enable register (ae 8 , ae 4 , ae 2 , ae 1 ) set a-s 1 to a-m 10 and a-w c d register it/pls 1 0 mask 1 1 c d register it/pls 2 0 mask 2 0 *1 from the viewpoint of software, the irq flag 1 bit is used. from the viewpoint of hardware, pin 1 (periodic out) is used for the msm6542-3 or pin 1 (interrup out) for the msm6542-1/2. *2 for the msm6542-1/2, a signal resulting from the oring with output triggered by an alarm is output to pin 1. when alarm factors are not required, the mask 2 bit must be set at 1. *3 the irq flag 1 bit is cleared. *1 from the viewpoint of software, the irq flag 2 bit is used. from the viewpoint of hardware, pin 2 (alarm out) is used for the msm6542-3 or pin 1 (interrupt out) for the msm6542-1/2. *2 for the msm6542-1/2, a signal resulting from the oring with output triggered by a periodic carry is output to pin 1. when periodic factors are not required, 1 must be set in the mask 1 bit. *3 time required to delete the previous output factors in the ic. *4 the irq flag 2 bit is cleared.
? semiconductor MSM6542-010/2/03 115 [setting interrupt conditions] perfomr the following setting with the dp bit set at 0. the set values are independent of the setting of the dp bit. (a) periodic interrupt output (*1) (b) alarm interrup output (*1) * 2 * 3 c d register it/pls 1 1 mask 1 1 set c d' register (*, cy 2 , cy 1 , cy 0 ) dummy readout of c e register c d register it/pls 1 1 mask 1 0 *1 from the viewpoint of software, the irq flag 1 bit is used. from the viewpoint of hardware, pin 1 (periodic out) is used for the msm6542- 03 or pin 1 (interrupt out) for the msm6542- 01/02. *2 for the msm6542-1/2, a signal resulting from the oring with output triggered by an alarm is output to pin 1. when alarm factors are not required, the mask 2 bit must be set at 1. *3 the irq flag 1 bit is cleared. *1 from the viewpoint of software, the irq flag 2 bit is used. from the viewpoint of hardware, pin 3 (alarm out) is used for the msm6542-03 or pin 1 (interrupt out) for the msm6542- 01/02. *2 for the MSM6542-01/02, a signal resulting from the oring with output triggered by a periodic carry is output to pin 1. when periodic factors are not required, 1 must be set in the mask 1 bit. *3 time required to output the previous interrupt factors *4 the irq flag 2 bit is cleared. c d register it/pls 2 1 mask 2 1 set a-s 1 to a-m 1o and a-w * 2 * 3 * 4 idling for 185 s set a-enable register dummy readout of c e register c d register it/pls 2 1 mask 2 0
? semiconductor MSM6542-01/02/03 116 [sensing interrupts] (a) when the dp bit is 0 interrupt y n another ic is an interrupt factor read c e register are both irq flag 1 and irq flag 2 bits 0 ? take action for irq flag 1 and irq flag 2 (b) when the dp bit is 1 read c e register id on cpu side take action for irq flag 1 and irq flag 2 are both irq flag 1 and irq flag 2 bits 0 ? irq flag 0 = 0 ie on cpu side another ic is an interrupt factor y n * 1 id: interrupt disable y n * 2 n y * 3 ie: interrupt enable interrupt read c e register are both irq flag 1 and irq flag 2 bits 0 ? read c e register *1 when the irq flag 1 and irq flag 2 bits are read, they are cleared. restoration of these pins to the open output status is delayed up to 122 m s. for this reason, the cpu is interrupt- disabled --- the cpu cannot accept interrupts. *2 when the maximum delay of 122 m s described in *1 elapses, the ira flag 0 bit is set at 0. *3 since hardware output re- questing an interrupt is re- stored to the open status, let the cpu interrupt enable.
? semiconductor MSM6542-010/2/03 117 [basic check at the early stage of development] (a) read/write check only the bank 1/0 bit can be subject to read and write operations without a paritcular procedure. the interface can be checked by reading and writing the bank 1/0 bit. check d3 = 0 read c f register c f (0, 0, 0, 0) r - s 1 (1, 1, 1, 1) *1 *2 *3 check d3 = 1 c f (1, 0, 0, 0) a - s 1 (0, 1, 1, 1) read c f register (b) checking oscillation using software oscillator operation can be checked using software through increment of clock registers, change of the irq flag 1 and irq flag 2 bits, 30-s adjustment, change of the read flag, and setting the dp bit at 0. these methods, except setting the dp bit at 0, affect the rest and stop bits. therefore, the method involved in the dp is used in the following flowcharts: c f register bank 1/0 1 c e' register dp 1 read c e' register dp 1 y n *1 *2 1 *1 (d3, d2, d1, d0) *2 use addresses and data having values opposite to those in *1 above to charge or discharge the bus in the reverse phase. *3 d3 is the bank 1/0 bit. *4 same idea as *2 *1, *2 the dp bit is not set at 1 for 62 m s after it changes from 1 to 0. when the step marked *2 is executed within the 62 m s interval but oscillation is in progress, the loop marked *1 is completed within 62 m s.
? semiconductor MSM6542-01/02/03 118 1 c e' register dp 0 idling for at least 11ms *2 *3 read c e' register dp = 0 ? y n oscillation is in progress *2 time until the dp bit becomes 0 under as- sumption that oscillation is in progress. *3 the time required for this loop is prolonged by the time equal to the one required to start oscillation. usually, this time is 0.5 to 2 s.
? semiconductor MSM6542-010/2/03 119 reference experimental data xt xt c g c d =32pf c g =12pf 10 20 6 234 5 6 v dd (v) ta = 25c 5 4 2 3 5 0 -5 80 ?/?(ppm) ta(c) -40 -20 0 20 40 60 -100 -50 ?/? (ppm) 40 20 -20 5 10 15 20 -40 -20 40 20 80 60 10 5 i dd (a) 0 ta (c) i dd (a) o dependency of oscillation frequency on power supply voltages o dependency of i dd on power supply voltages (ta = 25c) o dependency of oscillation frequency on temperatures o dependency of i dd on ambient temperatures o dependency of oscillation frequencies on capacitance note: the temperature characteristics of the capacitors used are class 0. crystral oscillator: p3 manufactured by kinseki co., ltd. (32.768 khz) load capacity: cl=12pf equivalent series resistance: 30k w (max) secondary temperature coefficient of frequency characteristics: -4.2 x 10 -8 /c (max) c d v dd v dd = 5v v dd = 3v v dd = 2v v dd = 2v v dd = 2v c d = 32pf v dd (v) c g (pf) ?/?(ppm) 0
? semiconductor MSM6542-01/02/03 120 package dimensions 18-pin plastic dip seating plane 1-pin index mark area 7.62 0.30 0.6 max 0~ 15 2.54 0.25 0.65 max 24.5 max 2.54 min 0.3 max 5.1 max 18 10 1 9 6.7 max (unit: mm) 24-pin plastic dip (unit: mm) 1-pin index mark area seating plane 14.2 max 15.24 0.30 0.6 max 0 ~ 15 2.54 0.25 0.65 max 0.3 min 5.1 max 32.3 max 2.54 min 1 9 10 24
? semiconductor MSM6542-010/2/03 121 20-pin plastic flat 1-pin index mark area 0 ~ 10 0.35 0.55 typ (unit: mm) 0 ~ 0.3 0.15 1.6 0.2 (unit: mm) 1-pin index mark area (gloss) 1.27 0.1 0.35 0.1 2.2 0.2 0.1 ~ 0.3 0 ~ 10 0.2 1.0 7.9 0.3 12.0 0.4 1.6 0.3 12 1 10 5.0 0.3 6.8 0.4 10.0 0.3 20 11 0.95 0.1 24 13 1 24-pin plastic flat

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